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Basic Design - "Hello GReasy"

HelloWorld GReasy Application

This section describes how to create a basic design with FPGA and GReasy.
Before continuing, make sure that GReasy enhanced GNU radio companion is installed on your machine with all the prerequisites.
By the end of the this tutorial, you'll have created a GReasy application, generated a bitstream with the backend assembly tools, TFlow, and programmed the device.

Figure 1. Finished design.


1. Open GNU Radio Companion. Open a terminal on your linux desktop and type "gnuradio-companion". If GNU Radio is installed, then this should autocomplete.
2. Create a blank GNU Radio design. At the top left, click the "Create a new flow graph" button.

Figure 1. Create new flow graph.

3. You should now have a blank and untitled flowgraph page in the GNU Radio window.

4. Notice the module block library on the right side of the window. At the top should be the AFPGA module block libraries. If

5. A GReasy based radio design that targets FPGAs has two distinct types of blocks: I/O Blocks and Processing blocks. I/O blocks represent the Static region of the hardware design and processing blocks are modules that can be placed in the sandbox or dynamic region of the hardware design. During design assembly, after a design has been built, these parts of the design are stitched together and precompiled.

6. To build your design, select the AFPGA ZYNQ sublibrary. This will expand in the library window. Then double click the aFPGA Zynq Linux In and aFPGA Zynq Linux Out blocks. These are the I/O blocks used for this tutorial since you've already set up your Zynq ZC7045 with embedded Linux running on the ARM.

7. Next select the aFPGA zynq passthrough block. This passthrough module will be placed in the sandbox design by TFlow when the flowgraph is compiled.

8. To complete the design, you can append any sink or source blocks you want to the input and output of the AFPGA I/O blocks. To get data streaming requires a bit of cleverness at this time, but to get a design up and running (the point of this tutorial) we won't worry about that just yet.

Figure 3. Execute the flowgraph.

9. Finally, when your design looks like the finished design given above click  "Execute the flowgraph", at the top center of the toolbar. During execution time, an EDIF netlist is compiled of the flowgraph design. That EDIF is input to TFLow, which generates a bitstream. Scripts that run in the background without user intervention handle these steps, including finally programming the device.

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Book | by Dr. Radut