The purpose of this document is to provide a GNU Radio user the necessary information needed to create a hardware object that can be instantiated into a GNU Radio design. The process presented here will transform the behaviour of an input design into a binary object, augmented with appropriate metadata. This object is then merged into the GNU Radio module block library, which then makes it available for design entry just as any other GNU Radio module block.
This document assumes that the reader is familiar with the general principles of GNU Radio. It also assumes that the reader is superficially familiar with FPGA design entry. If not, there are several useful tutorials available from Xilinx that do well in preparing for this tutorial. Component development is performed within a Linux environment. For software, any front-end software that is capable of generating an EDIF netlist can be used. For module creation, Xilinx ISE is needed along with the Partial Reconfiguration license. GReasy is dependent upon Boost and a few other Linux packages. It also depends on the open-source package, TORC, yet no explicit download is needed.
While any front-end tool can be used, this tutorial assumes that the component is specified as a Verilog file. While several devices and platforms are supported, it is assumed here that a Series-7 FPGA is targeted. In regards to software, Xilinx ISE 14.7 is used for component compilation, working in an Ubuntu 14.04 LTS desktop environment.