Radio technology is rapidly evolving and as processing capabilties and algorithms become more complex, the need for alternative compilation and user interface abstraction increases. Field Programmable Gate Array (FPGA) technology introduces unique reconfigurable hardware architectures that can aid in software defined radio (SDR) design. FPGAs have greater processing capability than traditional general purpose processors (GPP) found in desktop workstations. This work builds on an ongoing project, GReasy, that augments a Linux based open source SDR development platform, GNU Radio, with FPGA processing capabilties. By delegating processing intensive portions of a radio design to the Xilinx Zynq FPGA architec- ture, the domain of deployable radios by GNU Radio can be broadened. Xilinx Zynq, integrates the FPGA fabric and CPU onto a single chip, which eliminates the need for a controlling host computer; thus, providing a single, portable, low-power, embedded platform. GR-Easy is a Zynq capable version of GNU Radio – an open-source rapid radio deployment tool – with an enhanced flow that utilizes the processing capability of FPGAs. This work features TFlow – an FPGA back-end compilation accelerator for instant FPGA assembly. GReasy generates a description of the hardware components that are used by TFlow for the instant FPGA assembly. Once the FPGA is programmed with a design based on the description generated by GReasy, modules and the target hardware can be parameterized to realize an even larger class of applications and further solidify the concept of rapid assembly of software defined radios.
Fig. 1. Zynq-based GR-Easy processing node (FPGA in the loop) with 1G Ethernet interface and RF frontend.
Fig. 2. Example of the data link tracker implemented with GR-Easy.
Rapid Design Assembly
The current market is lacking a radio development environment that provides the best of both worlds – a rapid development and instant gratification environment combined with hardware acceleration of FPGAs. Rapid Design Assembly (RDA) paradigm extends the concept of rapid assembly of software-only components to a rapid assembly of hardware-software systems. Like GNU Radio, RDA relies upon highly optimized and parameterized hardware components. These components are pre-compiled FPGA objects in various shapes and forms in a proprietary relocatable format. When instanced in a radio design, these components are placed in the FPGA fabric, and a custom high-performance signal router connects the components. Since the components themselves are pre-compiled, the assembly process can be performed in just a few seconds, compared to the hours required by the FPGA vendor tools.
Fig. 3. FPGA-in-the-loop ruins radio designer productivity due to long compilation times (top). GR-Easy and TFlow-based Rapid Design Assembly technology provides software-like compilaton times for radio designs using FPGA components (bottom).
- Desktop processing node - use x86(Desktop) software modules. This is a normal GNU Radio mode
- Embedded ARM Node - software modules are executed on embedded ARM nodes.
- Augmented Software - modules accelerated in FPGA fabric. This is a normal GR-Easy mode
- Augmented ARM - embedded ARM accelerated with FPGA fabric
- Multi-Platform - scalable cluster of various FPGA families with peer-to-peer MGT/LVDS links
Fig. 4. GR-Easy computing cluster, 4x ZC702 Dev Kit connected using high-speed LVDS links.
- Virtex-5 XUP - V5LX110T
- Zynq ZC706 - ZC7045
- Zynq ZC702 / ZEDBOARD - ZC7020
- USRP x310 - Kintex 7K410T
- Dr. Peter Athanas
- Andrew Love
- Ryan Marlow
- Chris Dobson
- Kurt Rooks
- Richard Stroop
- Shaver Deyerle
- Dr. Krzysztof Kepa
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- T Frangieh, P Athanas, "A design assembly framework for FPGA back-end acceleration", Microprocessors and Microsystems, 2014
- R Marlow, P Athanas, "An Enhanced and Embedded FPGA GNU Radio Flow", Wireless Innovation Forum SDR-WinnComm, 2014.
- A Love, P Athanas, "Rapid modular assembly of Xilinx FPGA designs", Field Programmable Logic and Applications (FPL), 2013
- A Love, W Zha, P Athanas, "In pursuit of instant gratification for FPGA design", Field Programmable Logic and Applications (FPL), 2013
- W Zha, P Athanas, "An FPGA Router for Alternative Reconfiguration Flows", Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013
- W Zha, P Athanas, "Fine-Grained Manipulation of FPGA Configuration for Incremental Design", Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013
- A Love, P Athanas, "FPGA meta-data management system for accelerating implementation time with incremental compilation", Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, 2013
- R Stroop, P Athanas, "Enhancing GNU Radio For Run-time Assembly of FPGA-Based Accelerators", Wireless Innovation Forum SDR-WinnComm, 2014.
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- K Kepa, F Morgan, P Athanas, "ERDB: An embedded routing database for reconfigurable systems", Field Programmable Logic and Applications (FPL), 2011
- N Steiner, A Wood, H Shojaei, J Couch, P Athanas, "Torc: towards an open-source tool flow", ACM/SIGDA international symposium on Field programmable gate arrays, 2011
K Kępa, Fearghal Morgan, K Kościuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker, "Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems", ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2010